1. Technical Field
The subject matter described herein relates to analog-to-digital converters (ADCs). In particular, the subject matter described herein relates to time-interleaved ADCs.
2. Description of Related Art
Conventional time-interleaved ADCs (TI-ADCs), in which a plurality of sub-ADCs operate on time-synchronized samples, have limited operating frequency. Dominant factors restricting operating frequency include the number of sub-ADCs that process time-synchronized analog input data in parallel and clock misalignment between them. For example, to achieve a 7-bit ENOB (i.e., effective number of bits) analog-to-digital conversion of an 8 GHz analog input, time interleaved sampling clocks must be matched within a clock skew of only 100 fs (i.e., 100×10−15 seconds).
Clock skew or misalignment between sub-ADCs causes spurs in the output spectrum. Spurs degrade ADC performance, e.g., as indicated by spurious free dynamic range (SFDR), signal to noise and distortion ratio (SNDR) and the effective number of bits (ENOB). Thus, there is a general need to advance the state of the art and a specific need to improve clock alignment in time-interleaved ADCs.